Recently, various semiconductor memory devices such as the SRAM have been developed as semiconductor memory devices which write and read information at a high speed. The data is held in the SRAM as long as a predetermined power source voltage is maintained; further, no refresh operation is required, as in the case of a DRAM (dynamic random access memory). In the semiconductor memory devices such as the SRAM, there are demands to reduce the power consumption and to increase the operation speed.
As a conventional semiconductor memory device of this type, there is a single port SRAM shown in FIG. 1, for example. In this SRAM, Tn1 and Tn2 represent n-channel MOS transistors, INV1 and INV2 represent inverters, WL represents a word line, and BL and BL represent bit lines.
This SRAM uses the same bit lines BL and BL for writing and reading information. For this reason, the potentials of the bit lines BL and BL are held to the state of the write data after the write operation ends, and it takes almost no time to read out the data immediately after the write operation. However, because the same bit lines BL and BL are used for the write and read operations, there is a need to watch the change in the data (bit error) held by the memory cell. This bit error is a phenomenon in which the data held in the memory cell is inverted due to the load of the bit lines BL and BL when the word line WL is switched at the time of the data read out.
That is, in the SRAM of the type shown in FIG. 1, the word line WL and the bit lines BL and BL are respectively made up of several tens to several hundreds of aluminum lines, and the capacitance of the bit lines BL and BL is considerably large. For this reason, when the word line WL is switched, the potential difference of the bit lines BL and BL has a greater effect on the potentials of the n-channel MOS transistors Tn1 and Tn2 than the inverters INV1 and INV2 which invert the potentials of the n-channel MOS transistors Tn1 and Tn2, and there are cases where the above bit error occurs.
Conventionally, measures were taken against the bit error such as (1) reducing the potential difference of the bit lines BL and BL by pulling up the lower voltage level of the voltage levels applied to the bit lines BL and BL to approximately 2 V, for example, and (2) short-circuiting the bit lines BL and BL before switching the word line WL so as to eliminate the potential difference of the bit lines BL and BL.
However, according to the conventional method (1), the lower voltage level of the bit lines BL and BL is pulled up to approximately 2 V. As a result, a voltage is applied to the bit lines even when the voltage level corresponds to the low level, presenting problem of the power consumption increasing.
On the other hand, according to the conventional method (2), the bit lines BL and BL are short-circuited before switching the word line WL. For this reason, a signal for short-circuiting the bit lines BL and BL must be generated internally. Hence, even if an attempt is made to perform a read operation after the write operation ends, for example, a time margin is required to generate this signal, and there is a problem in that the operation speed deteriorates.
As a measure against the the above two problems, a SRAM shown in FIG. 2 has been proposed. In this SRAM, Tn3 and Tn4 represent n-channel MOS transistors, INV3 and INV4 represent inverters, WBL and WBL represent bit lines exclusively for writing, and RBL and RBL represent bit lines exclusively for reading.
In this SRAM, dividing the bit lines BL and BL into the bit lines WBL and WBL exclusively for reading and the bit lines RBL and RBL exclusively for reading eliminates the time margin required by the above conventional method (2) in order to internally generate the signal for short-circuiting the bit lines BL and BL. However, according to this structure in which the bit lines BL and BL are divided into the bit lines WBL and WBL exclusively for reading and the bit lines RBL and RBL exclusively for reading, a problem occurs if the capacitance of the bit lines BL and BL is large, that is, in the case of a large scale SRAM. In other words, when a write enable signal is changed from a low level to a high level and the read operation is carried out immediately after the write operation, the potentials of the n-channel MOS transistors Tn3 and Tn4 are inverted by the inverters INV3 and INV4 after the bit line potential on the write side is inverted when switching the word line WL, and it takes a considerably long time for the bit line potential on the read side to be inverted. As a result, when the data is read out immediately after the write operation, there are cases where the data before the write operation is carried out is read out, that is, the previous data before the potentials of the n-channel MOS transistors Tn3 and Tn4 are inverted is read out.
In FIG. 3, (a) shows an address signal, (b) shows the write enable signal, (c) shows the bit line potential on the write side, (d) shows the bit line potential on the read side, and (e) shows the output data of the memory.
Accordingly, a predetermined time interval must be provided before the read operation which is carried out immediately after the write operation, and there was a problem in that the access time becomes extremely long.